Makefiles:make is smart

Prev: Multiple independent targets

Till now to compile a c program we have passed the command to the makefile to compile a given c code. But make has built in intelligence and can work even without the command.

Let us say we have ta file

hello.c

#include<stdio.h> main() { printf("Hello world"); }

To compile this file using make we just need to create the makefile with the contents

makefile

hello:

make looks at the targets and if no dependencies and commands are mentioned in the makefile,it automatically looks for a file with the name .c i.e. in the above example hello.c and compiles it to create the executable.

$ make cc hello.c -o hello

If we want to make sure that the correct files are being compiled before actually generating the executable we can just print the commands that make is going to run by passing the option "--just-print".

$ make --just-print cc hello.c -o hello

In the above case the executable will not get generated, but it only prints the commands that will be executed.

We can also print the folders in which make is running the commands from using the option -w

$ make -w make: Entering directory `/home/user/temp' cc hello.c -o hello make: Leaving directory `/home/user/temp'

Next: Makefiles: Using variables