Makefiles: Using variables

Prev: make is smart We can use variables in makefile to prevent typing the same strings over and over and also make the file more easy to understand.

Defining variables: Let us say we have a makefile to compile three independent executables hello_1, hello_2 and hello_3

all: hello_1 hello_2 hello_3 hello_1:hello_1.c cc -o hello_1 hello_1.c hello_2:hello_2.c cc -o hello_2 hello_2.c hello_3:hello_3.c cc -o hello_3 hello_3.c

In the above makefile we use the string "cc -o" repeatedly. Instead of typing the whole string every time we can create a variable for it.
We can create a variable of any name by using the "=" sign. The left hand would be the name of the variable and the right hand side would be the value of the variable.
Any where in the file if we want to use the value of the variable we just have to use the name of the variable in the format $() and make will automatically replace the variable with its value while executing.

CC = cc -o all: hello_1 hello_2 hello_3 hello_1:hello_1.c $(CC) hello_1 hello_1.c hello_2:hello_2.c $(CC) hello_2 hello_2.c hello_3:hello_3.c $(CC) hello_3 hello_3.c

In the above file have created a variable CC and used it whenever we needed cc -o.
Note that variables are case sensitive thus "cc" "CC" and "Cc" are all different.
We can also use variables for prefixes of various strings. Like in the example above "hello" is like a prefix to a number of strings, thus we can use a variable for it.

CC = cc -o pf=hello all: $(pf)_1 $(pf)_2 $(pf)_3 $(pf)_1:$(pf)_1.c $(CC) $(pf)_1 $(pf)_1.c $(pf)_2:hello_2.c $(CC) $(pf)_2 $(pf)_2.c $(pf)_3:hello_3.c $(CC) $(pf)_3 $(pf)_3.c

Recursive expanded variables : We can create recursive variables by using one variable while declaring another.

CC = cc -o pf=hello targets = $(pf)_1 $(pf)_2 $(pf)_3 all: $(targets) $(pf)_1:$(pf)_1.c $(CC) $(pf)_1 $(pf)_1.c $(pf)_2:hello_2.c $(CC) $(pf)_2 $(pf)_2.c $(pf)_3:hello_3.c $(CC) $(pf)_3 $(pf)_3.c

In the above example "targets" is a variable, which is a list of all the targets. The targets variable uses the variable "pf" , thus to find out what $(targets) refers to make will have to expand pf creating a recursion among variables any depth of such recursion is allowed.
The limitation of defining variables using "=" is that a variable can not refer to itself in recursion.

CC = cc -o pf=hello targets = $(pf)_1 $(pf)_2 targets = $(targets) $(pf)_3 all: $(targets) $(pf)_1:$(pf)_1.c $(CC) $(pf)_1 $(pf)_1.c $(pf)_2:hello_2.c $(CC) $(pf)_2 $(pf)_2.c $(pf)_3:hello_3.c $(CC) $(pf)_3 $(pf)_3.c

In the above example, the second definition of variable "targets" uses the "targets" itself in recursion. Such usage will result in an infinite loop, which make successfully detects and throws the error.

makefile:5: *** Recursive variable `targets' references itself (eventually). Stop.

Simply expanded variables This can be prevented by making use of simply expanded variables which are defined using ":=". The use of ":=" makes the expansion of all the variables in the assignment only once and stop, thus preventing the infinite loop.

Thus in the above example the second definition should be

CC = cc -o pf=hello targets = $(pf)_1 $(pf)_2 targets := $(targets) $(pf)_3 all: $(targets) $(pf)_1:$(pf)_1.c $(CC) $(pf)_1 $(pf)_1.c $(pf)_2:hello_2.c $(CC) $(pf)_2 $(pf)_2.c $(pf)_3:hello_3.c $(CC) $(pf)_3 $(pf)_3.c

Now make will not throw any error and will successfully compile the targets.

Using shell in declaration : We can also execute shell commands while defining variables.

CC = cc -o pf=hello targets = $(pf)_1 $(pf)_2 targets := $(targets) $(pf)_3 opd = $(shell pwd) all: $(targets) $(pf)_1:$(pf)_1.c $(CC) $(opd)/$(pf)_1 $(pf)_1.c $(pf)_2:hello_2.c $(CC) $(pf)_2 $(pf)_2.c $(pf)_3:hello_3.c $(CC) $(pf)_3 $(pf)_3.c

In the above example we executed the command "pwd" and assigned the result to the variable "opd" which we used while compiling to indicate the path where the compiled executable needs to be stored.

Makefiles:make is smart

Prev: Multiple independent targets

Till now to compile a c program we have passed the command to the makefile to compile a given c code. But make has built in intelligence and can work even without the command.

Let us say we have ta file

hello.c

#include<stdio.h> main() { printf("Hello world"); }

To compile this file using make we just need to create the makefile with the contents

makefile

hello:

make looks at the targets and if no dependencies and commands are mentioned in the makefile,it automatically looks for a file with the name .c i.e. in the above example hello.c and compiles it to create the executable.

$ make cc hello.c -o hello

If we want to make sure that the correct files are being compiled before actually generating the executable we can just print the commands that make is going to run by passing the option "--just-print".

$ make --just-print cc hello.c -o hello

In the above case the executable will not get generated, but it only prints the commands that will be executed.

We can also print the folders in which make is running the commands from using the option -w

$ make -w make: Entering directory `/home/user/temp' cc hello.c -o hello make: Leaving directory `/home/user/temp'

Next: Makefiles: Using variables

Makefiles: Multiple independent targets

Prev: Multiple dependent targets

The make command when executed with out any arguments always tries to create the first target. But in one makefile we can specify as many independent targets as we want and then choose to create the specific targets .

Let us say we have two programs

hello_1.c

#include<stdio.h> main() { printf("Hello world"); }

hello_2.c

#include<stdio.h> main() { printf("Hello universe"); }

The above two are independent programs which can be compiled on the command line using

$ cc -o hello_1 hello_1.c $ cc -o hello_2 hello_2.c

The same can be done by creating a makefile with two targets "hello_1" and "hello_2".

makefile:

hello_1: hello_1.c cc -o hello_1 hello_1.c hello_2: hello_2.c cc -o hello_2 hello_2.c

Now if we run the command make

$ make cc -o hello_1 hello_1.c

We can see that if use the command make with no arguments the first target i.e. hello_1 gets crated. Now if we want to create the second target we will have to pass the second target to the make command as an argument.

$ make hello_2 cc hello_2.c -o hello_2

Thus we can specify any specific target we want to create as the argument to the command make.

If we want to option of creating all the independent targets with out specifying every target separately we add a target to the makefile and mention all the targets as the dependencies.

makefile:

all: hello_1 hello_2 hello_1: hello_1.c cc -o hello_1 hello_1.c hello_2: hello_2.c cc -o hello_2 hello_2.c

Now we can create hello_1 and hello_2 by running make with all as the target.

$ make all cc -o hello_1 hello_1.c cc -o hello_2 hello_2.c

Thus we can use makefile with multiple targets and selectively create the required targets or create all of them together.

Next: Makefiles: make is smart

Makefiles: Dependent targets

Prev: Makefiles : Introduction The makefiles can have as many targets as we want, and they could be dependent on another or independent.

Let us say we have the following codes
hello_main.c

#include<stdio.h> main() { print_hello(); }

print_hello.c

print_hello() { printf("Hello world \n"); }

The first program is calling a function declared in the second program. To compile these codes we can run the command

$ cc -o final hello_main.c print_hello.c

This can be broken down into the following steps
Creating the object code

$ cc -c hello_main.c $ cc -c print_hello.c

This will generate the object files "hello_main.o" and "print_hello.o"

Now we can club the object codes into one executable

$ cc -o hello hello_print_main.o print_hello.o

This will generate the final executable hello.

For creating the executable hello, hello_main.o and print_hello.o are the prerequisites.
Thus the makefile entry for target hello is

hello: hello_main.o print_hello.o cc -o hello hello_print_main.o print_hello.o

For creating the object codes, hello_main.o and print_hello.o are the targets and hello_main.c and print_hello.c are the prerequisites

Thus the make file entries for the two object codes is

hello_main.o: hello_main.c cc -c hello_main.c print_main.o: print_main.c cc -c print_main.c

Combining the above two we can create the full makefile

makefile:

hello: hello_main.o print_hello.o cc -o hello hello_main.o print_hello.o hello_main.o: hello_main.c cc -c hello_main.c print_hello.o: print_hello.c cc -c print_hello.c

Note the order in which the entries have been added. The final target is the first entry, the prerequisites for the final target are created by making them as targets in the subsequent entries.

Now run the command make

$ make cc -c -o hello_main.o hello_print.c cc -c print.c cc -o final hello_main.o print.o

We can see that make starts compiling from the first independent target hello_main.o then it compiles print_hello.o then it create the final executable using the two object files.

Now open the program print_hello.c and modify the print statement

print_hello() { printf("Hello world again"); }

Save the program and run the command make again.

$make cc -c hello_print.c cc -o hello hello_main.o hello_print.o

We can see that make compiled only the modified program and did not compile hello_main.c which was not modified after the executable "hello" was created.

The above split was shown just show the concept of dependent targets. We can compile the same code using the shorter makefile

makefie:

hello: hello_print.c print.c cc -o hello_print hello_print.c print.c

If you misspell any of the prerequisite names then make will throw an error and fail. For eg. if we create the above makefile with the file name hell_print.c

hello: hell_print.c print.c cc -o hello_print hello_print.c print.c

On running make we will get the error

make: *** No rule to make target `hell_print.c', needed by `hello'. Stop.

The above error indicates that the problem is with the file name "hell_print.c" as the makefile is unable to find a file with that name. Next: Makefiles :Multiple Independent targets

Makefiles: Introduction

Makefiles: Introduction Makefiles are the files used by the utility make. make helps in compiling a source code into an executable or automate execution of commands listed in the makefile.

Let us say we have a file "hello.c"

hello.c

#include<stdio.h> main() { printf("Hello world"); }

The usual compilation of this in linux using gcc is

$ cc hello.c -o hello

We can use a makefile to do the same compilation
The syntax of writing a makefile is

Target:prerequisite <One tab space> command

A makefile is comprised of

Target : The executable which has to be generated. In the above case the target is the executable hello.

Prerequisite: The source files required to generated the target. In the above example the source is hello.c

Command: If the prerequisite is available which command will convert it into the target ? The command in the above example is "cc -o hello.c -o hello". The command always has to be preceded by a single tab space

Create a file by the name "Makefile" and enter the contents

Makefile

hello:hello.c cc -o hello hello.c

Now open a terminal and cd to the folder where the makefile is stored.
Run the command

$ make cc -o hello hello.c

We can see that make has run the command and generated the executable just as we did from the command line.
You might get the following error if you have omitted the tab space before the command.

Makefile:2: *** missing separator. Stop.

If you name the makefile wrongly You might get the error

make: *** No targets specified and no makefile found. Stop.

The makefile can also be named with any other name we want but in that case we need to use the option "-f" with the command make. If we want to name the above makefile as my_makefile then we need to use the command make as make -f my_makefile

After the makefile has generated the executable if we run the command make again we will get the message

make: `hello' is up to date.

This is a special property of the make utility. It will generated a new executable of the mentioned target only if the target does not exist or the source file has been modified after the target has been generated. Next : Makefiles: Dependent targets

Extracting pages from a pdf file using linux command line

pdftk is a tool which we can use to split or extract pages from a pdf document.

To install pdfktk on debian based systems

sudo apt-get install pdftk

Let us say we have a pdf file,temp.pdf, with 100 pages in it. We want to extranct the pages 20 to 30 and create a new pdf . We can do it using pdftk

$ pdftk temp.pdf cat 20-30 output new.pdf

If the command returns to the prompt with no errors, we will have a new pdf file in the same directory with the name new.pdf.

We can pick specific pages instead of a range by just passing the page numbers.

To create a new pdf by extracting pages 21,25, and 28 we can use.

$ pdftk temp.pdf cat 21 25 28 output new.pdf

We can also select only even/odd pages by passing the option even/odd respectively

To extract all the odd numbered pages we can use the range as 1-end and use the keyword odd.

$pdftk temp.pdf cat 1-endodd

Truncate:Reduce file size from command line in linux

We can change the size of a file from the command line using the command truncate.

For e.g.

$ ls -lh -rw-r--r-- 1 nitin adm 7.3K Apr 5 2012 temp.txt -rw-r--r-- 1 nitin adm 9.4K Apr 5 2012 temp1.txt

We can change the size of temp1.txt to any size we need.

$ truncate -s 4k temp1.txt $ ls -rw-r--r-- 1 nitin adm 7.3K Apr 5 2012 temp.txt -rw-r--r-- 1 nitin adm 4.0K Apr 5 2012 temp1.txt

But be careful as the truncation simply removes the content of the file to reduce its size.